 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| dual port, xpressview, 3 ghz hdmi receiver data sheet adv7619 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2011C2015 analog devices, inc. all rights reserved. technical support www.analog.com features high-definition multimedia interface (hdmi?) 1.4a features supported all mandatory and additional 3d video formats supported extended colorimetry, including sycc601, adobe? rgb, adobe ycc601, xvycc extended gamut color cec 1.4-compatible hdmi 3 ghz receiver 297 mhz maximum tmds clock frequency supports 4k 2k resolution xpressview? fast switching of hdmi ports up to 48-bit deep color with 36-/30-/24-bit support high-bandwidth digital content protection (hdcp) 1.4 support with internal hdcp keys hdcp repeater support: up to 127 ksvs supported integrated cec controller programmable hdmi equalizer 5 v detect and hot plug? assert for each hdmi port audio support audio support including high bit rate (hbr) and direct stream digital (dsd) s/pdif (iec 60958-compatible) digital audio support supports up to four i 2 s outputs advanced audio mute feature dedicated, flexible audio output port super audio cd? (sacd) with dsd output interface hbr audio dolby? truehd dts-hd master audio? general interrupt controller with 2 interrupt outputs standard identification (stdi) circuit highly flexible, 48-bit pixel output interface 36-bit output for resolutions up to 1080p deep color 2 24-bit pass-through outputs for hdmi formats greater than 2.25 ghz internal edid ram any-to-any, 3 3 color space conversion (csc) matrix 128-lead tqfp_ep, 14 mm 14 mm package applications projectors video conferencing hdtv avr, htib soundbar video switch functional block diagram tmds ddc tmds ddc component processor hs/vs field/de clk data i 2 s s/pdif dsd hbr mclk hs vs/field de audio output mclk sclk clk 36-/48-bit output bus sclk lrclk 36 48 output mux output mux hdmi1 hdmi2 adv7619 09580-001 fast switch hdcp keys deep color hdmi rx figure 1.
adv7619 data sheet rev. d | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? general description ......................................................................... 3 ? detailed functional block diagram .......................................... 3 ? specifications ..................................................................................... 4 ? electrical characteristics ............................................................. 4 ? data and i 2 c timing characteristics ......................................... 6 ? absolute maximum ratings ............................................................ 8 ? package thermal performance ................................................... 8 ? esd caution .................................................................................. 8 ? pin configuration and function descriptions ............................. 9 ? power supply recommendations ................................................. 13 ? power-up sequence ................................................................... 13 ? power-down sequence .............................................................. 13 ? current rating requirements for power supply design ...... 13 ? functional overview ...................................................................... 14 ? hdmi receiver ........................................................................... 14 ? component processor (cp) ...................................................... 14 ? other features ............................................................................ 14 ? pixel input/output formatting .................................................... 15 ? pixel data output mode features ............................................ 15 ? outline dimensions ....................................................................... 22 ? ordering guide .......................................................................... 22 ? revision history 10/15rev. c to rev. d changes to table 3 ............................................................................ 6 added unit of measure to infrared reflow soldering parameter, table 4 and operating temperature range parameter, table 4 . 8 changes to ordering guide .......................................................... 22 1/14rev. b to rev. c changes to table 5 ............................................................................ 9 5/12rev. a to rev. b changes to features section............................................................ 1 changes to general description section and figure 2 ............... 3 change to table 1 ............................................................................. 4 changes to table 3 ............................................................................ 6 changes to figure 5; deleted figure 6, renumbered sequentially ....................................................................................... 7 changes to figure 7 ........................................................................... 9 changes to table 5 .......................................................................... 11 changes to hdmi receiver section and other features section .. 14 deleted time-division multiplexed (tdm) mode section and figure 9 ............................................................................................ 15 9/11rev. 0 to rev. a changes to general description section ...................................... 3 changes to data output transition time typ values, table 3 ... 6 changes to pin 113 description ................................................... 12 changes to pixel input/output formatting section .................. 16 added endnote 1 to table 7 .......................................................... 17 added endnote 1 to table 12 ........................................................ 22 changes to ordering guide .......................................................... 23 7/11revision 0: initial version data sheet adv7619 rev. d | page 3 of 24 general description the adv7619 is a high quality, two input, one output (2:1) multiplexed high-definition multimedia interface (hdmi?) receiver. the adv7619 is offered in professional (no hdcp keys) and commercial versions. the operating temperature range is 0c to 70c. the adv7619 incorporates a dual input hdmi-capable receiver that supports all mandatory 3d tv formats defined in the hdmi 1.4a specification, hdtv formats up to 1080p 36-bit deep color/2160p 8-bit, and display resolutions up to 4k 2k (3840 2160 at 30 hz). it integrates an hdmi cec controller that supports the capability discovery and control (cdc) feature. the adv7619 incorporates xpressview? fast switching on both input hdmi ports. using the analog devices, inc., hardware- based hdcp engine to minimize software overhead, xpressview technology allows fast switching between both hdmi input ports in less than 1 sec. each hdmi port has dedicated 5 v detect and hot plug? assert pins. the hdmi receiver also includes an integrated program- mable equalizer that ensures robust operation of the interface with long cables. the adv7619 offers a flexible audio output port for audio data extraction from the hdmi stream. hdmi audio formats, includ- ing sacd via dsd and hbr, are supported by the adv7619 . the hdmi receiver has advanced audio functionality, such as a mute controller, that prevents audible extraneous noise in the audio output. the adv7619 contains one main component processor (cp), which processes video signals from the hdmi receiver up to 1080p 36-bit deep color. it provides features such as contrast, brightness and saturation adjustments, stdi detection block, free-run, and synchronization alignment controls. for video formats with pixel clocks higher than 170 mhz, the video signals received on the hdmi receiver are output directly to the pixel port output. to accommodate the higher bandwidth required for these higher resolutions, the output on the pixel bus consists of two 24-bit buses running at up to 150 mhz: one bus contains the even pixels, and the other bus contains the odd pixels. when these two buses are combined, they allow the transfer of video data with pixel clocks up to 300 mhz. in this mode, both 4:4:4 rgb 8-bit and 4:2:2 12-bit are supported. fabricated in an advanced cmos process, the adv7619 is provided in a 14 mm 14 mm, 128-lead, surface-mount, rohs-compliant tqfp_ep package and is specified over the 0c to 70c temperature range. detailed functional block diagram 09580-002 mute xtalp xtaln scl sda cs cec ap1 ap2 ap3 ap4 ap5 ap0 sclk/int2* mclk/int2* int1 int2* p0 to p11 p12 to p23 p24 to p35 p36 to p47 llc hs vs/field/alsb de rxb_0 rxb_1 rxb_2 rxa_0 rxa_1 rxa_2 plls rxa_c rxb_c ddca_sda ddca_scl ddcb_sda ddcb_scl hpa_a/int2* hpa_b rxa_5v rxb_5v equalizer sampler equalizer hdcp engine hdcp keys edid repeater controller 5v detect and hdp controller cec controller control interface i 2 c dpll control and data 300mhz video path hdmi processor packet/ infoframe memory audio processor a b c component processor back-end color space conversion interrupt controller (int1, int2) data preprocessor and color space conversion packet processor *int2 can be made available on one of th ese pins: hpa_a/int2, mclk/int2, or sclk/int2. xpressview fast switching sampler adv7619 video output formatter audio output formatter figure 2. adv7619 data sheet rev. d | page 4 of 24 specifications electrical character istics dvdd = 1.7 1 v to 1.8 9 v, dvddio = 3.14 v to 3.46 v, pvdd = 1.71 v to 1.89 v, tvdd = 3.14 v to 3.46 v, cvdd = 1.71 v to 1.89 v, o perating temperature range, unless otherwise noted. table 1 . parameter symbol test conditions/comments min typ max unit digital inputs 1 input high voltage v ih xtaln and xtalp pins 1.2 v other digital inputs 2 v input low voltage v il xtaln and xtalp pins 0.4 v other digital inputs 0.8 v input current i in reset and cs pins 45 60 a oth er digital inputs 10 a input capacitance c in 10 pf digital inputs (5 v tolerant) 1 ddca_scl, ddca_sda, ddcb_scl, and ddcb_sda pins input high voltage v ih 2.6 v input low voltage v il 0.8 v input current i in ? 70 + 70 a digital outputs 1 output high voltage v oh 2.4 v output low voltage v ol 0.4 v high impedance leakage current i leak vs/field/alsb pin 35 60 a hpa_a/int2 and hpa_b pin s 70 a other dig ital outputs 10 a output capacitance c out 20 pf power requirements digital core power supply dvdd 1.71 1.8 1.89 v digital i/o power supply dvddio 3.14 3.3 3.46 v pll power supply pvdd 1.71 1.8 1.89 v terminator power supply tvdd 3.14 3.3 3.46 v comparator power supply cvdd 1.71 1.8 1.89 v current consumption see table 2 digital core power supply i dvdd test c ondition 1 268 ma test condition 2 186 ma digital i/o power supply i dvddio test c ondi tion 1 9 ma test condition 2 10 ma pll power supply i pvdd test c ondition 1 20 ma test condition 2 31 ma terminator power supply i tvdd test c ondition 1 92 ma test condition 2 92 ma comparator power supply i cvdd test c ondition 1 187 ma test c ondition 2 166 ma power - down current 2 see table 2 , test condition 3 digital core power supply i dvdd_pd 1.07 ma digital i/o power supply i dvddio_pd 0.034 ma pll power supply i pvdd_pd 0.691 ma term inator power supply i tvdd_pd 0.857 ma comparator power supply i cvdd_pd 0.053 ma power - up time t pwrup 25 ms 1 data guaranteed by characterization . 2 dat a recorded during lab characterization. data sheet adv7619 rev. d | page 5 of 24 table 2 . test conditions for current requirements parameter value u sed test condition 1 number of hdmi i nput s (xpressview mode) two inputs xpressview on video f ormat ( e ach hdmi i nput) 4k 2k hdcp d ecryption off video pattern ( e ach hdmi i nput ) smpte temperature 20 c power supply voltages nominal test condition 2 number of hdmi i nputs (xpressview mode) t wo inputs xpressview on video f ormat ( e ach hdmi i nput) 1080p60, 36 bits hdcp d ecryption off video pattern ( e ach hdmi i nput) smpte temperature 20c power supply voltages nominal test condition 3 (power - down) number of hdmi i nputs (xpressview mode) n/a xpressview n/a video f ormat ( e ach hdmi i nput) n/a hdcp d ecryption n/a video pattern ( e ach hdmi i nput) n/a temperature 20c power supply voltages nominal other t est p arameters power - down mode 0 (io map, reg ister 0x0c = 0x62) ring oscillator powe red down (hdmi map, reg ister 0x48 = 0x01) ddc pads powered off (hdmi map, reg ister 0x73 = 0x03) 1 1 for information about these registers, see the hardware user guide for the adv7619 ( ug - 237). adv7619 data sheet rev. d | page 6 of 24 data and i 2 c timing characteristics table 3. parameter symbol test conditions/comments min typ max unit clock and crystal crystal frequency, xtal 28.63636 mhz crystal frequency stability 50 ppm llc frequency range 13.5 170 mhz i 2 c ports scl frequency 400 khz scl minimum pulse width high 1 t 1 600 ns scl minimum pulse width low 1 t 2 1.3 s start condition hold time 1 t 3 600 ns start condition setup time 1 t 4 600 ns sda setup time 1 t 5 100 ns scl and sda rise time 1 t 6 300 ns scl and sda fall time 1 t 7 300 ns stop condition setup time 1 t 8 0.6 s reset feature reset pulse width 5 ms clock outputs 1, 2 llc mark-space ratio t 9 :t 10 for input video resolutions with a pixel clock frequency 170 mhz 45:55 55:45 % duty cycle for input video resolutions with a pixel clock frequency > 170 mhz 40:60 60:40 % duty cycle data and control outputs 1, 2 data output transition time t 11 end of valid data to negative llc edge 1.0 ns t 12 negative llc edge to start of valid data 0.1 ns i 2 s port, master mode 1 sclk mark-space ratio t 15 :t 16 45:55 55:45 % duty cycle lrclk data transition time t 17 end of valid data to negative sclk edge 10 ns t 18 negative sclk edge to start of valid data 10 ns i2sx data transition time t 19 end of valid data to negative sclk edge 5 ns t 20 negative sclk edge to start of valid data 5 ns 1 data guaranteed by characterization. 2 dll bypassed on clock path. timing diagrams 0 9580-003 sda scl t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 figure 3. i 2 c timing data sheet adv7619 rev. d | page 7 of 24 09580-004 t 9 llc p0 to p47, hs, v s/field/alsb, de t 11 t 12 t 10 figure 4. pixel port and control sdr output timing sclk lrclk i2sx left-justified mode i2sx right-justified mode i2sx i 2 smode msb msb ? 1 t 15 t 16 t 17 t 19 t 20 t 18 msb msb ? 1 lsb msb t 19 t 20 t 19 t 20 notes 1. the lrclk signal is available on the ap5 pin. 2. i2sx signals (where x = 0, 1, 2, or 3) are available on the following pins: ap1, ap2, ap3, and ap4. 09580-005 figure 5. i 2 s timing adv7619 data sheet rev. d | page 8 of 24 absolute maximum rat ings table 4 . parameter rating dvdd to gnd 2.2 v pvdd to gnd 2.2 v dvddio to gnd 4.0 v cvdd to gnd 2.2 v tvdd to gnd 4.0 v digital inputs to gnd gnd ? 0.3 v to dvddio + 0.3 v 5 v tolerant digital inputs to gnd 1 5.3 v digital outputs to gnd gnd ? 0.3 v to dvddio + 0.3 v xtalp, xtaln ?0.3 v to pvdd + 0.3 v scl , sda data pins to dvddio dvddi o ? 0.3 v to dvddio + 3.6 v maximum junction temperature (t j max ) 125 c storage temperature range ?60c to +150c operating temperature range 0c to 7 0c infrared reflow soldering (20 sec) 260 c 1 the following inputs are 3.3 v inputs but are 5 v tol erant: ddca_scl, ddca_sda, ddcb_scl, and ddcb_sda . stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other condition s above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. package thermal perf ormance to reduce power consumption when u sing the adv7619 , the user is advised to turn off the unused sections of the part. due to pcb metal variation and, therefore, variation in pcb heat conductivity, the value of ja may differ for v arious pcbs. the most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this solution eliminates the variance associated with the ja value. the maximum junction temperature (t j max ) of 125c must not be exceeded. the following equation calculates the junction temperature using the measured package surface temperature and applies only when no heat sink is used on the device under test (dut): t j = t s + ( jt w total ) where: t s is the pa ckage surface temperature (c). jt = 0.22c/w for the 128 - lead tqfp_ep . w total = (( pvdd i pvdd ) + (0. 2 tvdd i tvdd ) + ( cvdd i cvdd ) + ( dvdd i dvdd ) + ( dvddio i dvddio )) where 0. 2 is 20 % of the tvdd power that is dissipated on the part itself. esd caution data sheet adv7619 rev. d | page 9 of 24 pin configuration and fu nction descriptions 09580-008 notes 1. nc = no connect. do not connect to this pin. 2. connect the exposed pad (pin 0) on the bottom of the package to ground. 2 3 4 7 6 5 1 8 9 cvdd rxa_c? rxa_c+ rxa_0+ rxa_0? tvdd gnd tvdd rxa_1? 10 rxa_1+ 12 rxa_2? 13 rxa_2+ 14 cvdd 15 gnd 16 test1 17 dvdd 18 test2 19 cvdd 20 rxb_c? 21 rxb_c+ 22 tvdd 23 rxb_0? 24 rxb_0+ 25 tvdd 26 rxb_1? 27 rxb_1+ 28 tvdd 29 rxb_2? 30 rxb_2+ 31 cvdd 32 gnd 11 tvdd 95 vs/field/alsb 94 hs 93 de 90 p1 91 p0 92 dvddio 96 nc 89 p2 88 p3 87 p4 85 p6 84 p7 83 p8 82 p9 81 p10 80 p11 79 dvdd 78 p12 77 dvddio 76 p13 75 p14 74 p15 73 p16 72 p17 71 p18 70 p19 69 p20 68 p21 67 p22 66 p23 65 dvddio 86 p5 33 nc 34 dvdd 35 p47 36 p46 37 p45 38 p44 39 p43 40 dvddio 41 p42 42 p41 43 p40 44 p39 45 p38 46 p37 47 p36 48 p35 49 p34 50 p33 51 p32 52 dvddio 53 dvdd 54 p31 55 p30 56 p29 57 p28 58 p27 59 p26 60 p25 61 p24 62 llc 63 dvdd 64 dvdd 128 nc 127 nc 126 rxa_5v 125 hpa_a/int2 124 ddca_sda 123 ddca_scl 122 rxb_5v 121 hpa_b 120 ddcb_sda 119 ddcb_scl 118 cec 117 dvdd 116 xtaln 115 xtalp 114 pvdd 113 cs 112 reset 111 int1 110 scl 109 sda 108 dvdd 107 mclk/int2 106 ap5 105 sclk/int2 104 ap4 103 ap3 102 ap2 101 ap1 100 ap0 99 nc 98 nc 97 nc pin 1 adv7619 top view (not to scale) figure 6. pin configuration adv7619 data sheet rev. d | page 10 of 24 table 5 . pin function descriptions pin no. mnemonic type description 0 gnd ground ground . connect the exposed pa d (pin 0) on the bottom of the package to ground. 1 gnd ground ground. 2 cvdd power hdmi analog block supply voltage (1.8 v). 3 rxa_c ? hdmi input digital input clock complement of port a in the hdmi interface. 4 rxa_c+ hdmi input digital input clock true of port a in the hdmi interface. 5 tvdd power terminator supply voltage (3.3 v). 6 rxa_0 ? hdmi input digital input channel 0 comple ment of port a in the hdmi interface. 7 rxa_0+ hdmi input digital input channel 0 true of port a in the hdmi interface. 8 tvdd power terminator supply voltage (3.3 v). 9 rxa_1? hdmi input digital input channel 1 complement of port a in the hdmi interfac e. 10 rxa_1+ hdmi input digital input channel 1 true of port a in the hdmi interface. 11 tvdd power terminator supply voltage (3.3 v). 12 rxa_2? hdmi input digital input channel 2 complement of port a in the hdmi interface. 13 rxa_2+ hdmi input digital input channel 2 true of port a in the hdmi interface. 14 cvdd power hdmi analog block supply voltage (1.8 v). 15 gnd ground ground . 16 test1 test this pin must be left floating. 17 dvdd power digital core supply voltage (1.8 v) . 18 test2 test this pi n must be left floating. 19 cvdd power hdmi analog block supply voltage (1.8 v). 20 rxb_c ? hdmi input digital input clock complement of port b in the hdmi interface. 21 rxb_c+ hdmi input digital input clock true of port b in the hdmi interface. 22 tvdd power terminator supply voltage (3.3 v). 23 rxb_0? hdmi input digital input channel 0 com plement of port b in the hdmi interface. 24 rxb_0+ hdmi input digital input channel 0 true of port b in the hdmi interface. 25 tvdd power terminator supply voltage (3.3 v). 26 rxb_1? hdmi input digital input channel 1 complement of port b in the hdmi in terface. 27 rxb_1+ hdmi input digital input channel 1 true of port b in the hdmi interface. 28 tvdd power terminator supply voltage (3.3 v). 29 rxb_2? hdmi input digital input channel 2 complement of port b in the hdmi interface. 30 rxb_2+ hdmi input d igital input channel 2 true of port b in the hdmi interface. 31 cvdd power hdmi analog block supply voltage (1.8 v). 32 gnd ground ground . 33 nc no connect no c onnect . do not connect to this pin. 34 dvdd power digital core supply voltage (1.8 v) . 35 p 47 digital video output video pixel output port . 36 p46 digital video output video pixel output port . 37 p45 digital video output video pixel output port . 38 p44 digital video output video pixel output port . 39 p43 digital video output video pixel outp ut port . 40 dvddio power digital i/o supply voltage (3.3 v). 41 p42 digital video output video pixel output port . 42 p41 digital video output video pixel output port . 43 p40 digital video output video pixel output port . 44 p39 digital video output vid eo pixel output port . 45 p38 digital video output video pixel output port . 46 p37 digital video output video pixel output port . 47 p36 digital video output video pixel output port . 48 p35 digital video output video pixel output port . 49 p34 digital vi deo output video pixel output port . 50 p33 digital video output video pixel output port . 51 p32 digital video output video pixel output port . data sheet adv7619 rev. d | page 11 of 24 pin no. mnemonic type description 52 dvddio power digital i/o supply voltage (3.3 v). 53 dvdd power digital core supply voltage (1.8 v) . 54 p31 digital video output video pixel output port . 55 p30 digital video output video pixel output port . 56 p29 digital video output video pixel output port . 57 p28 digital video output video pixel output port . 58 p27 digital video output video pixel output port . 59 p26 digital video output video pixel output port . 60 p25 digital video output video pixel output port . 61 p24 digital video output video pixel output port . 62 llc digital video output pixel output clock for the pixel data . the r ange is from 1 3.5 mhz to 170 mhz. 63 dvdd power digital core supply voltage (1.8 v). 64 dvdd power digital core supply voltage (1.8 v). 65 dvddio power digital i/o supply voltage (3.3 v). 66 p23 digital video output video pixel output port . 67 p22 digital video out put video pixel output port . 68 p21 digital video output video pixel output port . 69 p20 digital video output video pixel output port . 70 p19 digital video output video pixel output port . 71 p18 digital video output video pixel output port . 72 p17 dig ital video output video pixel output port . 73 p16 digital video output video pixel output port . 74 p15 digital video output video pixel output port . 75 p14 digital video output video pixel output port . 76 p13 digital video output video pixel output por t . 77 dvddio power digital i/o supply voltage (3.3 v). 78 p12 digital video output video pixel output port . 79 dvdd power digital core supply voltage (1.8 v) . 80 p11 digital video output video pixel output port . 81 p10 digital video output video pixel output port . 82 p9 digital video output video pixel output port . 83 p8 digital video output video pixel output port . 84 p7 digital video output video pixel output port . 85 p6 digital video output video pixel output port . 86 p5 digital video output vi deo pixel output port . 87 p4 digital video output video pixel output port . 88 p3 digital video output video pixel output port . 89 p2 digital video output video pixel output port . 90 p1 digital video output video pixel output port . 91 p0 digital video output video pixel output port . 92 dvddio power digital i/o supply voltage (3.3 v). 93 de miscellaneous digital d ata e nable . the de signal indicates active pixel data. 94 hs digital video output h orizontal s ynchronization o utput s ignal. 95 vs/field/als b digital video output vs is a vertical synchronization output signal. field is a field synchronization output signal in all interlaced video modes . alsb allows selection of the i 2 c address. 96 nc no connect no c onnect . do not connect to this pin. 97 nc no connect no c onnect . do not connect to this pin. 98 nc no connect no c onnect . do not connect to this pin. 99 nc no connect no c onnect . do not connect to this pin. 100 ap0 miscellaneous audio output pin. this p in can be configured to output s/pdif d igi tal a udio, h igh b it r ate (hbr), or direct stream digital ? (dsd ? ) . 101 ap1 miscellaneous audio output pin. this pin can be configured to output s/pdif d igital audio , h igh b it r ate (hbr), d irect s tream d igital (dsd) . adv7619 data sheet rev. d | page 12 of 24 pin no. mnemonic type description 102 ap2 miscellaneous audio output pin. this pin can be configured to output s/pdif digital audio, high bit rate (hbr), direct stream digital (dsd), or i 2 s. 103 ap3 miscellaneous audio output pin. this pin can be configured to output s/pdif digital audio, high bit rate (hbr), direct stream dig ital (dsd), or i 2 s. 104 ap4 miscellaneous audio output pin. this pin can be configured to output s/pdif digital audio, high bit rate (hbr), direct stream digital (dsd), or i 2 s. 105 sclk/int2 miscellaneous digital serial clock/interrupt 2. this dual - funct ion pin can be configured to output the a udio serial c lock or an interrupt 2 signal. 106 ap5 miscellaneous audio output pin. this pin can be configured to output s/pdif digital audio, high bit rate (hbr), or direct stream digital (dsd). pin ap5 is typical ly used to provide the lrclk for i 2 s modes. 107 mclk/int2 miscellaneous digital master clock/interrupt 2. this dual - function pin can be configured to output the a udio m aster c lock or an interrupt 2 signal. 108 dvdd power digital core supply voltage (1.8 v). 109 sda miscellaneous digital i 2 c port serial data input/output pin. sda is the data line for the control port. 110 scl miscellaneous digital i 2 c port serial clock input. scl is the clock line for the control port. 111 int1 miscellaneous digital int errupt. this pin can be active low or active high. when status bits change, this pin is triggered. the events that trigger an interrupt are user con figurable . 112 reset miscellaneous digital system reset input. active low. a minimum low reset pulse width of 5 ms is required to reset the adv7619 circuitry. 113 cs miscellaneous digital chip select. this pin has an internal pull - down. pulling this line up caus es i 2 c state machine to ignore i 2 c transmission. 114 pvdd power pll supply voltage (1.8 v) . 115 xtalp miscellaneous input pin for 28.63636 mhz crystal or external 1.8 v, 28.63636 mhz clock oscillator source to clock the adv7619 . 116 xtaln miscellaneous crystal input. input pin for 28.63636 mhz crystal. 117 dvdd power digital core supply voltage (1.8 v) . 118 cec digital input/output consumer electronic s control channel. 119 ddcb_scl hdmi inpu t hdcp slave serial clock port b. ddcb_scl is a 3.3 v input that is 5 v tolerant. 120 ddcb_sda hdmi input hdcp slave serial data port b. ddcb_sda is a 3.3 v input that is 5 v tolerant. 121 hpa_b miscellaneous digital hot plug assert s ignal o utput for hdm i p ort b. this pin is 5 v tolerant. 122 rxb_5v hdmi input 5 v detect pin for port b in the hdmi interface. 123 ddca_scl hdmi input hdcp slave serial clock port a. ddca_scl is a 3.3 v input that is 5 v tolerant. 124 ddca_sda hdmi input hdcp slave serial data port a. ddca_sda is a 3.3 v input that is 5 v tolerant. 125 hpa_a/int2 miscellaneous digital hot plug assert/interrupt 2. this dual - function pin can be configured to output the hot plug a ssert signal for hdmi p ort a or an interrupt 2 signal. this pin is 5 v tolerant. 126 rxa_5v hdmi input 5 v detect pin for port a in the hdmi interface. 127 nc no connect no c onnect . do not connect to this pin. 128 nc no connect no c onnect . do not connect to this pin. data sheet adv7619 rev. d | page 13 of 24 power supply recommendations power-up sequence the recommended power-up sequence for the adv7619 is to power up the 3.3 v supplies first, followed by the 1.8 v supplies. reset should be held low while the supplies are powered up. alternatively, the adv7619 can be powered up by asserting all supplies simultaneously. in this case, care must be taken while the supplies are being established to ensure that a lower rated supply does not go above a higher rated supply level. 09580-007 3.3v supplies power supply (v) 3.3v supplies power-up 1.8v supplies power-up 3.3v 1.8v 1.8v supplies figure 7. recommended power-up sequence power-down sequence the adv7619 supplies can be deasserted simultaneously as long as a higher rated supply does not go below a lower rated supply. current rating requirements for power supply design table 6 shows the current rating requirements for power supply design. table 6. current rating requirements for power supply design parameter current rating (ma) i dvdd 400 i dvddio 300 i pvdd 50 i tvdd 120 i cvdd 250 adv7619 data sheet rev. d | page 14 of 24 functional overview hdmi receiver the hdmi receiver supports all mandatory and many optional 3d video formats d efined in the hdmi 1.4a specification, hdtv formats up to 2160p , and all display resolu tions up to 4k 2k (3840 2160 a t 30 hz). with the inclusion of hdcp, displays can now receive encrypted video content. the hdmi interface of the adv7619 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during trans - mission, as specified by the hdcp 1.4 specification . the hdmi - c o mpatible receiver on the adv7619 allows active equalization of the hdmi data signals. this equalization compen - sates for the high frequency losses inherent in hdmi and dvi cabling, especially at longer cable lengths and higher frequencies. the hdmi - compatible receiver is capable of equalizing for cable lengths up to 30 meters to achieve robust receiver performance. the adv7619 also suppo rts terc4 error detection, which is used for detection of corrupted hdmi packets following a cable disconnect. the hdmi receiver offers advanced audio functionality. the receiver contains an audio mute controller that can detect a variety of conditions tha t may result in audible extrane ous noise in the audio output. upo n detection of these conditions, the audio signal can be ramped down or muted to prevent audio clicks or pops. the hdmi receiver support s the reception of all types of audio data described in the hdmi specifications , including ? l pcm (uncompressed audio) ? iec 61937 (compressed audio) ? dsd audio ( 1 - bit audio) ? hbr audio (high bit rate compressed audio) xpressview fast switching can be implemented with full hdcp authentication available on the backgr ound port. synchroniza - tion measurement and status information are available for all hdmi inputs. hdmi receiver features include ? 2:1 multiplexed hdmi receiver ? 3d f ormat su pport ? 297 mhz hdmi receiver ? support for 4k 2 k resolutions ? integrated equalizer for cable lengths up to 30 meters ? high - bandwidth digital content protection (hdcp 1.4) ( on background ports , also ) ? internal hdcp keys ? 36- /30 - bit deep color support (resolutions up to 1080p) ? audio s ample, hbr, dsd packet support ? repeater support ? internal edid r am ? hot plug a ssert output pin for each hdmi port ? cec c ontroller component processor (cp) the adv7619 has two any - to - any , 3 3 color space conversion ( csc ) matrices. the first csc block is placed in front of the cp section. the second csc block is placed at the back of the cp section. each csc enables yprpb - to - rgb and rgb - to - ycrcb conversions. many other standards of color space can be imple - mented us ing the color space converters. the cp block is available only for video signals with resolution up to 1080p deep color (pixel rates up to 170 mhz) . for resolu - tions higher than 1080p, the video signal bypasses the cp block and is routed directly to the pixel bus output as two 24 - bit (4:4:4) buses runn ing at up to 150 mhz. cp features include ? support for 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, a nd many other hdtv formats ? manual adjustments including gain (contrast) , offset (brightness), hue , and saturation ? free - run output mode that provides stable timing when no video input is present ? 170 mhz conversion rate, which supports rgb input resolut ions up to 1600 1200 at 60 hz ? standard identification enabled by stdi block ? rgb that can be color space converted to ycrcb and decima ted to a 4:2:2 format for video - centric, back - end ic interfacing ? data enable (de) output signal supplied for direct connection to hdmi/dvi transmitter other features the adv7619 has hs, vs, field, and de output signals with programmable position, polarity, and width. the adv7619 has two programmable interrupt request output pins: int1 and int2 (int2 is accessible via one of the following pins: mclk/int2, sclk/i nt2, or hpa_a/int2). the adv7619 also features a low power power - down mode. the main i 2 c address ca n be set to 0x98 or 0x9a . on power - up or a fter a reset, t he i 2 c address is set to 0x98 by defaul t . th e address can be changed to 0x9a by pulling up the vs/field/alsb pin and issuing the i 2 c command sample_alsb. for more infor - mation, see the register access and serial ports description section in the ug - 237. the adv7619 is provided in a 128 - lead , 14 mm 14 mm, rohs - compliant tqfp_ep package an d is specified over the 0c to 70c temperature range. data sheet adv7619 rev. d | page 15 of 24 pixel input/output f ormatting the output section of the adv7619 is highly flexible. the pixel output bus can s upport up to 36 - bit 4:4:4 ycrcb or 36 - bit 4:4:4 rgb. f or resolu tions higher than 1080p, the pixel output bus s uppo rts two 24 - bit 4:4:4 rgb/ycrcb. part supports sdr (single data rate) and double data rate (ddr) outputs. sdr is supported up to 170 mhz llc frequency (uxga, 1080p60 for any op_format_sel or up to 300 mhz hdmi signals output on two 24 - bit parallel video su b buses op_format_sel = 0x94, 0x95, 0x96 , or 0x54; refer to table 12). ddr can be supported with llc clock frequency up to 50 mhz (video modes with original pixel clock lower than 100 mhz, such as 1080i60). in sdr mode, 16- /20 - / 2 4 - bit 4:2:2 or 24 - /30 - /36 - bit 4:4:4 output is possible. in ddr mode, the pixel output port can be configured for 4:2:2 ycrcb or 4:4:4 rgb for data rates up to 27 mhz. bus rotation is supported . table 7 through table 12 provide the different output formats that are supported. all output modes are controlled via i 2 c. for resolutions higher than 1080p , the video signa ls are routed directly to the pixel bus output as two 24 - bit (4:4:4) buses running at up to 150 mhz. in this mode, the output data format is the same as the input format. pixel data output mo de features for resolutions up to 1080p deep color , t he output pixel port features include the following: ? sdr 8 - /10 - /12 - bit itu - r bt.656 4:2:2 ycrcb with emb ed - ded time codes and/or hs, vs, and field output s ignals ? sdr 16 - /20 - /24 - bit 4:2:2 ycrcb with embedded time codes and/or hs and vs/field pin timing ? sdr 24- /30 - /36 - bit 4:4:4 ycrcb/rgb with embedded time codes and/or hs and vs/field pin timing ? ddr 8 - /10 - /12 - bit 4:2:2 ycrcb for data rates up to 27 mhz ? ddr 12 - /24 - /30 - /36 - bit 4:4:4 rgb for data rates up to 27 mhz for resolutions greater than 1080 p deep color ( d irect p ass - through of v ideo s ignal ) , t he output pixel port features include the following: ? 8 - bit 4:4:4 rgb/ycrcb for resolutions up to 2160p ? 12- bit 4:2:2 rgb/ycrcb for resolutions up to 2160p adv7619 data sheet rev. d | page 16 of 24 table 7 . sdr 4:2:2 output modes (8 - /10 - /12- bit) 1 sdr 4:2:2 op_format_sel[7:0] = 0x 0 0 0x 0 1 0x 0 2 0x 0 6 0x0a pixel output 8 - bit sdr itu - r bt.656 mode 0 10 - bit sdr itu - r bt.656 mode 0 12 - bit sdr itu - r bt.656 mode 0 12 - bit sdr itu - r bt.656 mode 1 12 - bit sdr itu - r bt.656 mode 2 p47 high - z high - z high - z high - z high - z p46 high - z high - z high - z high - z high - z p45 high - z high - z high - z hi gh - z high - z p44 high - z high - z high - z high - z high - z p43 high - z high - z high - z high - z high - z p42 high - z high - z high - z high - z high - z p41 high - z high - z high - z high - z high - z p40 high - z high - z high - z high - z high - z p39 high - z high - z high - z high - z high - z p38 high - z high - z high - z high - z high - z p37 high - z high - z high - z high - z high - z p36 high - z high - z high - z high - z high - z p35 high - z high - z high - z high - z y3, cb3, cr3 p34 high - z high - z high - z high - z y2, cb2, cr2 p33 high - z high - z high - z high - z y1, cb1, cr1 p 32 high - z high - z high - z high - z y0, cb0, cr0 p31 high - z high - z high - z high - z high - z p30 high - z high - z high - z high - z high - z p29 high - z high - z high - z y1, cb1, cr1 high - z p28 high - z high - z high - z y0, cb0, cr0 high - z p27 high - z high - z high - z high - z high - z p26 high - z high - z high - z high - z high - z p25 high - z high - z high - z high - z high - z p24 high - z high - z high - z high - z high - z p23 y7, cb7, cr7 y9, cb9, cr9 y11, cb11, cr11 y11, cb11, cr11 y11, cb11, cr11 p22 y6, cb6, cr6 y8, cb8, cr8 y10, cb10, cr10 y10, cb10, cr10 y10, cb10, cr10 p21 y5, cb5, cr5 y7, cb7, cr7 y9, cb9, cr9 y9, cb9, cr9 y9, cb9, cr9 p20 y4, cb4, cr4 y6, cb6, cr6 y8, cb8, cr8 y8, cb8, cr8 y8, cb8, cr8 p19 y3, cb3, cr3 y5, cb5, cr5 y7, cb7, cr7 y7, cb7, cr7 y7, cb7, cr7 p18 y2, cb2, cr2 y4, cb 4, cr4 y6, cb6, cr6 y6, cb6, cr6 y6, cb6, cr6 p17 y1, cb1, cr1 y3, cb3, cr3 y5, cb5, cr5 y5, cb5, cr5 y5, cb5, cr5 p16 y0, cb0, cr0 y2, cb2, cr2 y4, cb4, cr4 y4, cb4, cr4 y4, cb4, cr4 p15 high - z y1, cb1, cr1 y3, cb3, cr3 y3, cb3, cr3 high - z p14 high - z y0, cb0, cr0 y2, cb2, cr2 y2, cb2, cr2 high - z p13 high - z high - z y1, cb1, cr1 high - z high - z p12 high - z high - z y0, cb0, cr0 high - z high - z p11 high - z high - z high - z high - z high - z p10 high - z high - z high - z high - z high - z p 9 high - z high - z high - z high - z high - z p 8 high - z high - z high - z high - z high - z p 7 high - z high - z high - z high - z high - z p 6 high - z high - z high - z high - z high - z p 5 high - z high - z high - z high - z high - z p 4 high - z high - z high - z high - z high - z p 3 high - z high - z high - z high - z high - z p 2 high - z high - z hig h - z high - z high - z p 1 high - z high - z high - z high - z high - z p 0 high - z high - z high - z high - z high - z 1 modes require additional writes to io map register 0x19 (bits [7:6] should be set to 2'b11) and io map register 0x33 (bit [6] should be set to 1 ) . data sheet adv7619 rev. d | page 17 of 24 table 8 . sdr 4:2:2 output modes (16 - /20 - /24 - bit) sdr 4:2:2 op_format_sel[7:0] = 0x80 0x81 0x82 0x86 0x8a pixel output 16- bit sdr itu - r bt.656 mode 0 20- bit sdr itu - r bt.656 mode 0 24- bit sdr itu - r bt.656 mode 0 24- bit sdr itu - r bt.656 mode 1 24- bit sdr itu - r bt.656 mode 2 p47 high -z high -z high -z high -z high -z p46 high -z high -z high -z high -z high -z p45 high -z high -z high -z high -z high -z p44 high -z high -z high -z high -z high -z p43 high -z high -z high -z high -z high -z p42 high -z high -z high -z high -z high -z p41 high -z high -z high -z high -z high -z p40 high -z high -z high -z high -z high -z p39 high -z high -z high -z high -z high -z p38 high -z high -z high -z high -z high -z p37 high -z high -z high -z high -z high -z p36 high -z high -z high -z high -z high -z p35 high - z high - z high - z high - z y3 p34 high -z high -z high -z high -z y2 p33 high -z high -z high -z cb1, cr1 y1 p32 high -z high -z high -z cb0, cr0 y0 p31 high -z high -z high -z high -z cb3, cr3 p30 high -z high -z high -z high -z cb2, cr2 p29 high -z high -z high -z y1 cb1, cr1 p28 high -z high -z high -z y0 cb0, cr0 p27 high -z high -z high -z high -z high -z p26 high -z high -z high -z high -z high -z p2 5 high -z high -z high -z high -z high -z p24 high -z high -z high -z high -z high -z p23 y7 y9 y11 y11 y11 p22 y6 y8 y10 y10 y10 p21 y5 y7 y9 y9 y9 p20 y4 y6 y8 y8 y8 p19 y3 y5 y7 y7 y7 p18 y2 y4 y6 y6 y6 p17 y1 y3 y5 y5 y5 p16 y0 y2 y4 y4 y4 p15 high -z y 1 y3 y3 high -z p14 high -z y0 y2 y2 high -z p13 high -z high -z y1 high -z high -z p12 high -z high -z y0 high -z high -z p11 cb7, cr7 cb9, cr9 cb11, cr11 cb11, cr11 cb11, cr11 p10 cb6, cr6 cb8, cr8 cb10, cr10 cb10, cr10 cb10, cr10 p 9 cb5, cr5 cb7, cr7 cb9, cr 9 cb9, cr9 cb9, cr9 p 8 cb4, cr4 cb6, cr6 cb8, cr8 cb8, cr8 cb8, cr8 p 7 cb3, cr3 cb5, cr5 cb7, cr7 cb7, cr7 cb7, cr7 p 6 cb2, cr2 cb4, cr4 cb6, cr6 cb6, cr6 cb6, cr6 p 5 cb1, cr1 cb3, cr3 cb5, cr5 cb5, cr5 cb5, cr5 p 4 cb0, cr0 cb2, cr2 cb4, cr4 cb4, cr4 cb4, cr4 p 3 high -z cb1, cr1 cb3, cr3 cb3, cr3 high -z p 2 high -z cb0, cr0 cb2, cr2 cb2, cr2 high -z p 1 high -z high -z cb1, cr1 high -z high -z p 0 high -z high -z cb0, cr0 high -z high -z adv7619 data sheet rev. d | page 18 of 24 table 9 . sdr 4:4:4 output modes sdr 4:4:4 op_for mat_sel[7:0] = 0x40 0x41 0x42 0x46 pixel output 24- bit sdr mode 0 30- bit sdr mode 0 36- bit sdr mode 0 36- bit sdr mode 1 p47 high -z high -z high -z high -z p46 high -z high -z high -z high -z p45 high -z high -z high -z high -z p44 high -z high -z high -z high -z p43 high -z high -z high -z high -z p42 high -z high -z high -z high -z p41 high -z high -z high -z high -z p40 high -z high -z high -z high -z p39 high -z high -z high -z high -z p38 high -z high -z high -z high -z p37 high -z high -z high -z high -z p36 high -z high -z hig h -z high -z p35 r7 r9 r11 r9 p34 r6 r8 r10 r8 p33 r5 r7 r9 r7 p32 r4 r6 r8 r6 p31 r3 r5 r7 r5 p30 r2 r4 r6 r4 p29 r1 r3 r5 r3 p28 r0 r2 r4 r2 p27 high - z r1 r3 r1 p26 high -z r0 r2 r0 p25 high -z high -z r1 g7 p24 high -z high -z r0 g6 p23 g7 g9 g11 g5 p22 g6 g8 g10 g4 p21 g5 g7 g9 g3 p20 g4 g6 g8 g2 p19 g3 g5 g7 g1 p18 g2 g4 g6 g0 p17 g1 g3 g5 b11 p16 g0 g2 g4 b10 p15 high - z g1 g3 b9 p14 high -z g0 g2 b8 p13 high -z high -z g1 g11 p12 high -z high -z g0 g10 p11 b7 b9 b11 b7 p10 b6 b8 b10 b6 p 9 b5 b7 b9 b5 p 8 b4 b6 b8 b4 p 7 b3 b5 b7 b3 p 6 b2 b4 b6 b2 p 5 b1 b3 b5 b1 p 4 b0 b2 b4 b0 p 3 high -z b1 b3 r11 p 2 high -z b0 b2 r10 p 1 high -z high -z b1 g9 p 0 high -z high -z b0 g8 data sheet adv7619 rev. d | page 19 of 24 table 10 . ddr 4:2:2 output modes ddr 4:2:2 m ode (clock/2) op_format_sel[7:0] = 0x20 0x21 0x22 pixel output 8 - bit ddr itu - r bt.656, mode 0 10- bit ddr itu - r bt.656, mode 0 12- bit ddr itu - r bt.656, mode 0 clock rise clock fall clock rise clock fall clock rise clock fall p47 high -z high -z high -z h igh -z high -z high -z p46 high -z high -z high -z high -z high -z high -z p45 high -z high -z high -z high -z high -z high -z p44 high -z high -z high -z high -z high -z high -z p43 high -z high -z high -z high -z high -z high -z p42 high -z high -z high -z high -z high -z high -z p41 high -z high -z high -z high -z high -z high -z p40 high -z high -z high -z high -z high -z high -z p39 high -z high -z high -z high -z high -z high -z p38 high -z high -z high -z high -z high -z high -z p37 high - z high - z high - z high - z high - z high - z p36 high -z high -z hig h -z high -z high -z high -z p35 high -z high -z high -z high -z high -z high -z p34 high -z high -z high -z high -z high -z high -z p33 high -z high -z high -z high -z high -z high -z p32 high -z high -z high -z high -z high -z high -z p31 high - z high - z high - z high - z high - z hig h - z p30 high -z high -z high -z high -z high -z high -z p29 high -z high -z high -z high -z high -z high -z p28 high -z high -z high -z high -z high -z high -z p27 high -z high -z high -z high -z high -z high -z p26 high -z high -z high -z high -z high -z high -z p25 high -z high -z high -z high -z high -z high -z p24 high -z high -z high -z high -z high -z high -z p23 cb7, cr7 y7 cb9, cr9 y9 cb11, cr11 y11 p22 cb6, cr6 y6 cb8, cr8 y8 cb10, cr10 y10 p21 cb5, cr5 y5 cb7, cr7 y7 cb9, cr9 y9 p20 cb4, cr4 y4 cb6, cr6 y6 cb8, cr8 y8 p19 cb3, cr3 y3 cb5, cr5 y5 cb7, cr7 y7 p18 cb2, cr2 y2 cb4, cr4 y4 cb6, cr6 y6 p17 cb1, cr1 y1 cb3, cr3 y3 cb5, cr5 y5 p16 cb0, cr0 y0 cb2, cr2 y2 cb4, cr4 y4 p15 high -z high -z cb1, cr1 y1 cb3, cr3 y3 p14 high -z high -z cb0, cr0 y0 cb2, cr2 y2 p13 high -z hig h -z high -z high -z cb1, cr1 y1 p12 high -z high -z high -z high -z cb0, cr0 y0 p11 high -z high -z high -z high -z high -z high -z p10 high -z high -z high -z high -z high -z high -z p 9 high -z high -z high -z high -z high -z high -z p 8 high -z high -z high -z high -z high -z hi gh -z p 7 high -z high -z high -z high -z high -z high -z p 6 high -z high -z high -z high -z high -z high -z p 5 high -z high -z high -z high -z high -z high -z p 4 high -z high -z high -z high -z high -z high -z p 3 high - z high - z high - z high - z high - z high - z p 2 high -z high -z hig h -z high -z high -z high -z p 1 high -z high -z high -z high -z high -z high -z p 0 high -z high -z high -z high -z high -z high -z adv7619 data sheet rev. d | page 20 of 24 table 11 . ddr 4:4:4 output modes ddr 4:4:4 mode (clock/2) op_format_sel[7:0] = 0x60 0x61 0x62 pixel output 24- bit ddr , mode 0 30- bit ddr, mode 0 36- bit ddr, mode 0 clock rise 1 clock fall 1 clock rise 1 clock fall 1 clock rise 1 clock fall 1 p47 high -z high -z high -z high -z high -z high -z p46 high - z high - z high - z high - z high - z high - z p45 high -z high -z high -z high -z h igh -z high -z p44 high -z high -z high -z high -z high -z high -z p43 high -z high -z high -z high -z high -z high -z p42 high -z high -z high -z high -z high -z high -z p41 high - z high - z high - z high - z high - z high - z p40 high -z high -z high -z high -z high -z high -z p39 hig h -z high -z high -z high -z high -z high -z p38 high -z high -z high -z high -z high -z high -z p37 high -z high -z high -z high -z high -z high -z p36 high -z high -z high -z high -z high -z high -z p35 r7 -0 r7 -1 r9 -0 r9 -1 r11 - 0 r11 - 1 p34 r6 -0 r6 -1 r8 -0 r8 -1 r10 - 0 r10 - 1 p 33 r5 -0 r5 -1 r7 -0 r7 -1 r9 -0 r9 -1 p32 r4 -0 r4 -1 r6 -0 r6 -1 r8 -0 r8 -1 p31 r3 -0 r3 -1 r5 -0 r5 -1 r7 -0 r7 -1 p30 r2 -0 r2 -1 r4 -0 r4 -1 r6 -0 r6 -1 p29 r1 - 0 r1 - 1 r3 - 0 r3 - 1 r5 - 0 r5 - 1 p28 r0 -0 r0 -1 r2 -0 r2 -1 r4 -0 r4 -1 p27 high -z high -z r1 -0 r1 -1 r3 -0 r3 -1 p26 high -z high -z r0 -0 r0 -1 r2 -0 r2 -1 p25 high -z high -z high -z high -z r1 -0 r1 -1 p24 high - z high - z high - z high - z r0 - 0 r0 - 1 p23 g7-0 g7-1 g9-0 g9-1 g11- 0 g11- 1 p22 g6-0 g6-1 g8-0 g8-1 g10- 0 g10- 1 p21 g5-0 g5-1 g7-0 g7-1 g9-0 g9-1 p20 g4-0 g4-1 g6-0 g6-1 g8-0 g 8 -1 p19 g3-0 g3-1 g5-0 g5-1 g7-0 g7-1 p18 g2-0 g2-1 g4-0 g4-1 g6-0 g6-1 p17 g1-0 g1-1 g3-0 g3-1 g5-0 g5-1 p16 g0-0 g0-1 g2-0 g2-1 g4-0 g4-1 p15 high -z high -z g1-0 g1-1 g3-0 g3-1 p14 high -z high -z g0-0 g0-1 g2-0 g2-1 p13 high -z high -z high -z high -z g 1 -0 g1-1 p12 high -z high -z high -z high -z g0-0 g0-1 p11 b7 -0 b7 -1 b9 -0 b9 -1 b11 -0 b11 -1 p10 b6 -0 b6 -1 b8 -0 b8 -1 b10 -0 b10 -1 p 9 b5 -0 b5 -1 b7 -0 b7 -1 b9 -0 b9 -1 p 8 b4 - 0 b4 - 1 b6 - 0 b6 - 1 b8 - 0 b8 - 1 p 7 b3 - 0 b3 - 1 b5 - 0 b5 - 1 b7 - 0 b7 - 1 p 6 b2 -0 b2 -1 b4 -0 b4 -1 b6 -0 b6 -1 p 5 b1 -0 b1 -1 b3 -0 b3 -1 b5 -0 b5 -1 p 4 b0 -0 b0 -1 b2 -0 b2 -1 b4 -0 b4 -1 p 3 high -z high -z b1 -0 b1 -1 b3 -0 b3 -1 p 2 high -z high -z b0 -0 b0 -1 b2 -0 b2 -1 p 1 high -z high -z high -z high -z b1 -0 b1 -1 p 0 high -z high -z high -z high -z b0 -0 b0 -1 1 x x - 0 and xxx - 0 cor respond to data clocked at the rising edge ; xx - 1 and xxx - 1 correspond to data clocked at the falling edge . data sheet adv7619 rev. d | page 21 of 24 table 12 . special sdr 4:2:2 and 4:4:4 output modes for v ideo with pi xel c lock f requencies a bove 170 mhz 1 2 sdr 4:2:2 inte rleaved op_format_sel[7:0] = 2 sdr 4:4:4 interleaved op_format_sel[7:0] = 0x94 0x95 0x96 0x54 pixel output 2 16 - bit mode 0 2 2 20 - bit mode 0 2 2 24 - bit mode 0 2 2 24 - bit mode 0 2 p47 y7- 0 y9- 0 y11- 0 g7 - 0 p46 y6- 0 y8- 0 y10- 0 g6 - 0 p45 y5- 0 y7- 0 y9- 0 g5 - 0 p44 y4- 0 y6- 0 y8- 0 g4 - 0 p43 y3- 0 y5- 0 y7- 0 g3 - 0 p42 y2- 0 y4- 0 y6- 0 g2 - 0 p41 y1- 0 y3- 0 y5- 0 g1 - 0 p40 y0- 0 y2- 0 y4- 0 g0 - 0 p39 high - z y1- 0 y3- 0 b7 - 0 p38 high - z y0- 0 y2- 0 b6 - 0 p37 high - z high - z y1- 0 b5 - 0 p36 high - z high - z y0- 0 b4 - 0 p35 cb7 - 0 cb9 - 0 cb11 - 0 b3 - 0 p34 cb6 - 0 cb8 - 0 cb10 - 0 b2 - 0 p33 cb5 - 0 cb7 - 0 cb9 - 0 b1 - 0 p32 cb4 - 0 cb6 - 0 cb8 - 0 b0 - 0 p31 cb3 - 0 cb5 - 0 cb7 - 0 r7 - 0 p30 cb2 - 0 cb4 - 0 cb6 - 0 r6 - 0 p29 cb1 - 0 cb3 - 0 cb5 - 0 r5 - 0 p28 cb0 - 0 cb2 - 0 cb4 - 0 r4 - 0 p27 high - z cb1 - 0 cb3 - 0 r3 - 0 p26 high - z cb0 - 0 cb2 - 0 r2 - 0 p25 high - z high - z cb1 - 0 r1 - 0 p24 high - z high - z cb0 - 0 r0 - 0 p23 y7- 1 y9- 1 y11- 1 g7 - 1 p22 y6 - 1 y8 - 1 y10 - 1 g6 - 1 p21 y5- 1 y7- 1 y9- 1 g5 - 1 p20 y4- 1 y6- 1 y8- 1 g4 - 1 p19 y3- 1 y5- 1 y7- 1 g3 - 1 p18 y2- 1 y4- 1 y6- 1 g2 - 1 p17 y1 - 1 y3 - 1 y5 - 1 g1 - 1 p16 y0- 1 y2- 1 y4- 1 g0 - 1 p15 high - z y1- 1 y3- 1 b7 - 1 p14 high - z y0- 1 y2- 1 b6 - 1 p13 high - z high - z y1- 1 b5 - 1 p12 high - z high - z y0- 1 b4 - 1 p11 cr7 - 0 cr9 - 0 cr11 - 0 b3 - 1 p10 cr6 - 0 cr8 - 0 cr10 - 0 b2 - 1 p 9 cr5 - 0 cr7 - 0 cr9 - 0 b1 - 1 p 8 cr4 - 0 cr6 - 0 cr8 - 0 b0 - 1 p 7 cr3 - 0 cr5 - 0 cr7 - 0 r7 - 1 p 6 cr2 - 0 cr4 - 0 cr6 - 0 r6 - 1 p 5 cr1 - 0 cr3 - 0 cr5 - 0 r5 - 1 p 4 cr0 - 0 cr2 - 0 cr4 - 0 r4 - 1 p 3 high - z cr1 - 0 cr3 - 0 r3 - 1 p 2 high - z cr0 - 0 cr2 - 0 r2 - 1 p 1 high - z high - z cr1 - 0 r1 - 1 p 0 high - z high - z cr0 - 0 r0 - 1 1 these modes r equire additional writes. ( write 80 to dpll map register 0xc3, write 03 to dpll map register 0xcf, and write a0 to io map register 0xdd ). refer to hardware user guide ug - 237. 2 x x - 0 and xxx - 0 correspond to odd samples; xx - 1 and xxx - 1 correspond to even sam ples. adv7619 data sheet rev. d | page 22 of 24 outline dimensions compliant to jedec standards ms-026-aee-hd top view (pins down) bottom view (pins up) exposed pad 1 32 33 64 97 128 96 65 0.23 0.18 0.13 pin 1 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 6.35 ref 12.40 ref for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 10-06-2011-a 0.08 coplanarity 7 0 view a rotated 90 ccw 1.05 1.00 0.95 0.15 0.10 0.05 0.20 0.15 0.09 view a 1.20 max seating plane 0.75 0.60 0.45 1.00 ref 32 33 64 97 128 1 0.40 bsc lead pitch 65 96 figure 8. 128-lead thin quad flat package, exposed pad [tqfp_ep] (sv-128-1) dimensions shown in millimeters ordering guide model 1, 2 temperature range package description package option adv7619ksvz 0c to 70c 128-lead thin quad flat package, exposed pad [tqfp_ep] sv-128-1 adv7619ksvz-p 0c to 70c 128-lead thin quad flat package, exposed pad [tqfp_ep] sv-128-1 EVAL-ADV7619-7511-p evaluation board without hdcp keys EVAL-ADV7619-7511 evaluation board with hdcp keys 1 z = rohs compliant part. 2 EVAL-ADV7619-7511 and EVAL-ADV7619-7511 -p are rohs compliant parts. data sheet adv7619 rev. d | page 23 of 24 notes adv7619 data sheet rev. d | page 24 of 24 notes i 2 c refers to a communications protocol originally developed by p hilips semiconductors (now nxp semiconductors). hdmi, the hdmi logo, and high - definition multimedia interface are trademarks or registered trademarks of hdmi licensing llc in the united states and other countries. ? 2011 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09580 - 0 - 10/15(d) |
Price & Availability of EVAL-ADV7619-7511
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |